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M12L128324A-5BG2C - 1M x 32 Bit x 4 Banks Synchronous DRAM

General Description

The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle) M12L128324A (2C) 1M x 32 Bit x 4 Banks Synchronous DRAM.

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Other Datasheets by ESMT (Elite Semiconductor Microelectronics Technology)

Part Number Description
M12L128324A-5BG2E Synchronous DRAM
M12L128324A-5TG2C 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A-6BG2C 1M x 32 Bit x 4 Banks Synchronous DRAM
M12L128324A-6BG2E Synchronous DRAM
M12L128324A-6TG2C 1M x 32 Bit x 4 Banks Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ESMT SDRAM FEATURES  JEDEC standard 3.3V power supply  LVTTL compatible with multiplexed address  Four banks operation  MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave)  All inputs are sampled at the positive going edge of the system clock  DQM for masking  Auto & self refresh  64ms refresh period (4K cycle) M12L128324A (2C) 1M x 32 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L128324A-5BG2C M12L128324A-6BG2C M12L128324A-7BG2C Max Freq. 200MHz Package 90 FBGA Comments Pb-free 166MHz 90 FBGA Pb-free 143MHz 90 FBGA Pb-free GENERAL DESCRIPTION The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.