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M12L128324A-7BG2E - Synchronous DRAM

This page provides the datasheet information for the M12L128324A-7BG2E, a member of the M12L128324A-5BG2E Synchronous DRAM family.

Description

The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L128324A (2E) 1M x 32 Bit x 4 Banks Synchronous DRAM.

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Datasheet Details

Part number M12L128324A-7BG2E
Manufacturer ESMT
File Size 964.71 KB
Description Synchronous DRAM
Datasheet download datasheet M12L128324A-7BG2E Datasheet
Additional preview pages of the M12L128324A-7BG2E datasheet.

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Full PDF Text Transcription

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ESMT SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L128324A (2E) 1M x 32 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L128324A-5BG2E M12L128324A-6BG2E M12L128324A-7BG2E Max Freq. 200MHz Package 90 FBGA Comments Pb-free 166MHz 90 FBGA Pb-free 143MHz 90 FBGA Pb-free GENERAL DESCRIPTION The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
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