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M12L128324A-7TG2C - 1M x 32 Bit x 4 Banks Synchronous DRAM

This page provides the datasheet information for the M12L128324A-7TG2C, a member of the M12L128324A 1M x 32 Bit x 4 Banks Synchronous DRAM family.

Description

The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle) M12L128324A (2C) 1M x 32 Bit x 4 Banks Synchronous DRAM.

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Datasheet Details

Part number M12L128324A-7TG2C
Manufacturer ESMT
File Size 1.11 MB
Description 1M x 32 Bit x 4 Banks Synchronous DRAM
Datasheet download datasheet M12L128324A-7TG2C Datasheet
Additional preview pages of the M12L128324A-7TG2C datasheet.

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Full PDF Text Transcription

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ESMT SDRAM FEATURES  JEDEC standard 3.3V power supply  LVTTL compatible with multiplexed address  Four banks operation  MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave)  All inputs are sampled at the positive going edge of the system clock  DQM for masking  Auto & self refresh  64ms refresh period (4K cycle) M12L128324A (2C) 1M x 32 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L128324A-5TG2C M12L128324A-6TG2C M12L128324A-7TG2C Max Freq. Package Comments 200MHz 86 TSOPII Pb-free 166MHz 86 TSOPII Pb-free 143MHz 86 TSOPII Pb-free GENERAL DESCRIPTION The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
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