M12L64164A-5BIG2C Datasheet | Elite Semiconductor Microelectronics Technology

FEATURES - JEDEC standard 3.3V power supply - LVTTL patible with multiplexed address - Four banks operation - MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) - All inputs are sampled at the positive going edge of the system clock - DQM for masking - Auto & self refresh - 64ms refresh period (4K cycle) - 15.6  s refresh interval M12L64164A (2C) Operation Temperature Condition -40~85°C 1M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L64164A-5TIG2C M12L64164A-7TIG2C M12L64164A-5BIG2C M12L64164A-7BIG2C Max Freq. Package ments 200MHz 54 TSOP II Pb-free 143MHz 54 TSOP II Pb-free 200MHz 54 VBGA Pb-free 143MHz 54 VBGA Pb-free GENERAL DESCRIPTION The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN CONFIGURATION (TOP VIEW) (TSOPII 54L, 400mil X875mil Body, 0.8mm Pin Pitch) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mm X8mm X1mm Body, 0.8mm Ball Pitch) VDD 1 DQ0 2 VDDQ 3 DQ1 4 DQ2 5 VSSQ 6 DQ3 7 DQ4 8 VDDQ 9 DQ5 10 DQ6 11 VSSQ 12 DQ7 13 VDD 14 LDQM 15 W E 16 CAS 17 RAS 18 CS 19 BA0 20 BA1 21 A10/AP 22 A0 23 A1 24 A2 25 A3 26 VDD 27 54 VSS 53 DQ15 52 VSSQ 51 DQ14 50 DQ13 49 VDDQ 48 DQ12 47 DQ11 46 VSSQ 45 DQ10 44 DQ9 43 VDDQ 42 DQ8 41 VSS 40 NC 39 UDQM 38 CLK 37 CKE 36 NC 35 A11 34 A9 33 A8 32 A7 31 A6 30 A5 29 A4 28 VSS VSS DQ15 VSSQ VDDQ DQ0 VDD DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4...