M13S64164A-5BG Datasheet PDF (1M x 16 Bit x 4 Banks Double Data Rate SDRAM)

M13S64164A-5BG - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

Download the M13S64164A-5BG datasheet PDF (M13S64164A-5TG included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 1m x 16 bit x 4 banks double data rate sdram.

Features

z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe.

Datasheet Details

Part number	M13S64164A-5BG
Manufacturer	ESMT
File Size	1.51 MB
Description	1M x 16 Bit x 4 Banks Double Data Rate SDRAM
Datasheet	M13S64164A-5BG Datasheet

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Full PDF Text Transcription

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ESMT M13S64164A DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS) z DQS is edge-aligned with data for reads; center-aligned with data for WRITE z Data mask (DM) for write masking only z VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.

Published: Mar 25, 2019 |