M13S64164A-5TG2Y Datasheet PDF (1M x 16 Bit x 4 Banks Double Data Rate SDRAM)

M13S64164A-5TG2Y - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

Download the M13S64164A-5TG2Y datasheet PDF (M13S64164A included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 1m x 16 bit x 4 banks double data rate sdram.

Features

z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Four bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock (CLK) z Data I/O transitions on both edges of data strobe (DQS) z DQS is edge-aligned with data for REA.

📥 Download Datasheet

M13S64164A-5TG2Y 1m x 16 bit x 4 banks double data rate sdram by ESMT - Datasheet Preview — Note: The manufacturer provides a single datasheet file (M13S64164A_EliteSemiconductorMemoryTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	M13S64164A-5TG2Y
Manufacturer	ESMT
File Size	1.19 MB
Description	1M x 16 Bit x 4 Banks Double Data Rate SDRAM
Datasheet	M13S64164A-5TG2Y Datasheet

📁 Similar Datasheet

M13S128168A - Double Data Rate SDRAM (Elite Semiconductor Memory Technology)

M13S2561616A - 4M x 16 Bit x 4 Banks Double Data Rate SDRAM (Elite Semiconductor Memory Technology)

M13S256328A - 2M x 32 Bit x 4 Banks Double Data Rate SDRAM (Elite Semiconductor Memory Technology)

M13S32321A - 256K x 32 Bit x 4 Banks Double Data Rate SDRAM (Elite Semiconductor Memory Technology)

M13 - TECHNICAL SPECIFICATIONS OF SURFACE MOUNT SILICON RECTIFIER (Dc Components)

M1302L - S-band Magnetron (Nisshinbo)

M1325 - Surface Mount Crystal (MTRONPTI)

M132C - CDS OSH & ON/OFF Melody IC (MOSDESIGN)

M133C - CDS OSH & ON/OFF Melody IC (MOSDESIGN)

M133NWF2-R0 - TFT LCD (IVO)

Full PDF Text Transcription

Click to expand full text

ESMT M13S64164A (2Y) DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Four bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock (CLK) z Data I/O transitions on both edges of data strobe (DQS) z DQS is edge-aligned with data for READs; center-aligned with data for WRITEs z Data mask (DM) for write masking only z VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V z 15.6us refresh interval z Auto & Self refresh z 2.

Published: Mar 25, 2019 |