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M13S64164A-5TG2C - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

Download the M13S64164A-5TG2C datasheet PDF. This datasheet also covers the M13S64164A-4TG2C variant, as both devices belong to the same 1m x 16 bit x 4 banks double data rate sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

DM is an input mask signal for write data.

Key Features

  • Double-data-rate architecture, two data transfers per clock cycle.
  • Bi-directional data strobe (DQS).
  • Differential clock inputs (CLK and CLK ).
  • DLL aligns DQ and DQS transition with CLK transition.
  • Four bank operation.
  • CAS Latency : 2, 3.
  • Burst Type : Sequential and Interleave.
  • Burst Length : 2, 4, 8.
  • All inputs except data & DM are sampled at the rising edge of the system clock (CLK).
  • Data I/O transitions on both edges of data strobe (DQS).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M13S64164A-4TG2C-ESMT.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by ESMT (Elite Semiconductor Microelectronics Technology)

Part Number Description
M13S64164A-5TG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-5TG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-5BG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-5BG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-4BG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ESMT M13S64164A (2C) DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features  Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK )  DLL aligns DQ and DQS transition with CLK transition  Four bank operation  CAS Latency : 2, 3  Burst Type : Sequential and Interleave  Burst Length : 2, 4, 8  All inputs except data & DM are sampled at the rising edge of the system clock (CLK)  Data I/O transitions on both edges of data strobe (DQS)  DQS is edge-aligned with data for READs; center-aligned with data for WRITEs  Data mask (DM) for write masking only  VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V  15.6us refresh interval  Auto & Self refresh  2.