M14D1G1664A - DDR-II SDRAM

Datasheet Summary

Description

Pin Name A0~A12, BA0~BA2 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS) ODT NC Function Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP : Auto Precharge BA0~BA2 : Bank selects (8 Banks) Data-in/Data-out Command input Command input Command input Ground Power Bi-direc

Features

JEDEC Standard.
VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V.
Internal pipelined double-data-rate architecture; two data access per clock cycle.
Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
On-chip DLL.
Differential clock inputs (CLK and CLK ).
DLL aligns DQ and DQS transition with CLK transition.
8 bank operation.
CAS Latency : 3, 4, 5, 6, 7.
Additive Latency: 0, 1, 2, 3, 4, 5, 6.

ESMT

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Datasheet Details

Part number	M14D1G1664A
Manufacturer	ESMT
File Size	1.98 MB
Description	DDR-II SDRAM
Datasheet	M14D1G1664A Datasheet
Additional preview pages of the M14D1G1664A datasheet.

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Full PDF Text Transcription

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ESMT DDR II SDRAM M14D1G1664A (2P) 8M x 16 Bit x 8 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

Published: Sep 20, 2018 |