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M14D2561616A-2.5BG2S - DDR-II SDRAM

This page provides the datasheet information for the M14D2561616A-2.5BG2S, a member of the M14D2561616A DDR-II SDRAM family.

Description

Ball Name A0~A12, BA0,BA1 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS ) ODT NC Function Address inputs - Row address A0~A12 - Column address A0~A8 A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Command input Command input Command input Ground Power Bi-di

Features

  • JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition 1KB page size - Row address: A0 to A12 - Column address: A0 to A8 Quad bank operation CAS Latency : 3, 4, 5, 6, 7, 8, 9 Additive Latency: 0, 1, 2,.

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Datasheet Details

Part number M14D2561616A-2.5BG2S
Manufacturer ESMT
File Size 1.05 MB
Description DDR-II SDRAM
Datasheet download datasheet M14D2561616A-2.5BG2S Datasheet
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ESMT DDR II SDRAM (Preliminary) M14D2561616A (2S) 4M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
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