Download the M14D2561616A-2.5BIG2C datasheet PDF.
This datasheet also covers the M14D2561616A-1.5BIG2C variant, as both devices belong to the same ddr ii sdram family and are provided as variant models within a single manufacturer datasheet.
Description
M14D2561616A (2C)
Operation Temperature Condition -40°C~95°C
Ball Name
A0~A12, BA0,BA1
DQ0~DQ15 RAS CAS WE VSS VDD
DQS, DQS (LDQS, LDQS UDQS, UDQS )
ODT
NC
Function
Address inputs - Row address A0~A12 - Column address A0~A8 A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-ou
Features
- JEDEC Standard.
- VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V.
- Internal pipelined double-data-rate architecture; two data access per clock cycle.
- Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
- On-chip DLL.
- Differential clock inputs (CLK and CLK ).
- DLL aligns DQ and DQS transition with CLK transition.
- 1KB page size
- Row address: A0 to A12 - Column address: A0 to A8.
- Quad bank operation.
M14D2561616A-2.5BIG2C Datasheet
