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M14D5121632A-1.5BG2S - 8M x 16 Bit x 4 Banks DDR II SDRAM

General Description

Pin Name A0~A12, BA0,BA1 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS ) ODT NC Function Pin Name Function Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks) DM (LDM, UDM) DM is an input mask signal for write data

Key Features

  • JEDEC Standard.
  • VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V.
  • Internal pipelined double-data-rate architecture; two data access per clock cycle.
  • Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
  • On-chip DLL.
  • Differential clock inputs (CLK and CLK ).
  • DLL aligns DQ and DQS transition with CLK transition.
  • Quad bank operation.
  • CAS Latency : 3, 4, 5, 6, 7, 8, 9.
  • Additive Latency: 0, 1, 2, 3, 4,.

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Other Datasheets by ESMT (Elite Semiconductor Microelectronics Technology)

Part Number Description
M14D5121632A-1.5BG2A DDR-II SDRAM
M14D5121632A-1.5BG2M 8M x 16 Bit x 4 Banks DDR II SDRAM
M14D5121632A-1.8BBG2A DDR-II SDRAM
M14D5121632A-1.8BBG2M 8M x 16 Bit x 4 Banks DDR II SDRAM
M14D5121632A-1.8BBG2S 8M x 16 Bit x 4 Banks DDR II SDRAM

Full PDF Text Transcription (Reference)

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ESMT M14D5121632A (2S) DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.