Datasheet4U Logo Datasheet4U.com

M15F1G1664A - 8M x 16 Bit x 8 Banks DDR3 SDRAM

General Description

The 1Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAM.

The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank devices.

Key Features

  • and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages. DDR3 SDRAM Addressing Configuration M15F1G1664A # of Bank 8 Bank Address BA0.
  • BA2 Auto precha.

📥 Download Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ESMT M15F1G1664A (2C) DDR3 SDRAM Feature  Interface and Power Supply  SSTL_15: VDD/VDDQ = 1.5V(±0.