M52D5123216A-6BG
Description
The M52D5123216A is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 32 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle.
Key Features
- 1.8V power supply
- LVCMOS compatible with multiplexed address
- Four banks operation
- MRS cycle with address key programs - CAS Latency (2, 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave)
- EMRS cycle with address
- All inputs are sampled at the positive going edge of the system clock
- Special function support - PASR (Partial Array Self Refresh) - TCSR (Temperature Compensated Self Refresh) - DS (Driver Strength) - Deep Power Down (DPD) Mode
- DQM for masking
- Auto & self refresh
- 64ms refresh period (8K cycle)
