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QL2009-2PQ208C - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility

Download the QL2009-2PQ208C datasheet PDF. This datasheet also covers the QL2 variant, as both devices belong to the same 3.3v and 5.0v pasic 2 fpga combining speed/ density/ low cost and flexibility family and are provided as variant models within a single manufacturer datasheet.

General Description

Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-d

Key Features

  • -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (QL2-009.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number QL2009-2PQ208C
Manufacturer Unknown Manufacturer
File Size 272.83 KB
Description 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
Datasheet download datasheet QL2009-2PQ208C Datasheet

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Other Datasheets by Unknown Manufacturer

Part Number Description
QL2009-2PQ208I 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-2PB256C 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-2PB256I 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-2PF144C 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
QL2009-2PF144I 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev.