EBE11UD8AESA Overview
The EBE11UD8AESA is 128M words × 64 bits, 2 ranks DDR2 SDRAM Small Outline Dual In-line Memory Module, mounting 16 pieces of 512M bits DDR2 SDRAM sealed in FBGA (µBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4 bits prefetch-pipelined architecture.
EBE11UD8AESA Key Features
- 200-pin socket type small outline dual in line memory module (SO-DIMM) PCB height: 30.0mm Lead pitch: 0.6mm Lead-f
- Power supply: VDD = 1.8V ± 0.1V
- Data rate: 667Mbps/533Mbps/400Mbps (max.)
- SSTL_18 patible I/O
- Double-data-rate architecture: two data transfers per clock cycle
- Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data
- DQS is edge aligned with data for READs: centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge: data and data mask referenced to both edges of DQS