EBE52UC8AAFV Overview
The EBE52UC8AAFV is 64M words × 64 bits, 2 ranks DDR2 SDRAM unbuffered module, mounting 16 pieces of 256M bits DDR2 SDRAM sealed in FBGA package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4 bits prefetch-pipelined architecture.
EBE52UC8AAFV Key Features
- 240-pin socket type dual in line memory module (DIMM) PCB height: 30.0mm Lead pitch: 1.0mm Lead-free
- 1.8V power supply
- Data rate: 700Mbps/667Mbps/600Mbps (max.)
- 1.8V (SSTL_18 patible) I/O
- Double-data-rate architecture: two data transfers per clock cycle
- Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data
- DQS is edge aligned with data for READs: centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge: data and data mask referenced to both edges of DQS