EBE52UC8AAFV - 512MB Unbuffered DDR2 SDRAM HYPER DIMM

Description

The EBE52UC8AAFV is 64M words × 64 bits, 2 ranks DDR2 SDRAM unbuffered module, mounting 16 pieces of 256M bits DDR2 SDRAM sealed in FBGA package.

Read and write operations are performed at the cross points of the CK and the /CK.

Features

240-pin socket type dual in line memory module (DIMM)  PCB height: 30.0mm  Lead pitch: 1.0mm  Lead-free.
1.8V power supply.
Data rate: 700Mbps/667Mbps/600Mbps (max. ).
1.8V (SSTL_18 compatible) I/O.
Double-data-rate architecture: two data transfers per clock cycle.
Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver.
DQS is edge aligned with data f.

Elpida Memory

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Datasheet Details

Part number	EBE52UC8AAFV
Manufacturer	Elpida Memory
File Size	231.02 KB
Description	512MB Unbuffered DDR2 SDRAM HYPER DIMM
Datasheet	EBE52UC8AAFV Datasheet
Additional preview pages of the EBE52UC8AAFV datasheet.

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Full PDF Text Transcription

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PRELIMINARY DATA SHEET www.DataSheet4U.com 512MB Unbuffered DDR2 SDRAM HYPER DIMM EBE52UC8AAFV (64M words × 64 bits, 2 Ranks) Description The EBE52UC8AAFV is 64M words × 64 bits, 2 ranks DDR2 SDRAM unbuffered module, mounting 16 pieces of 256M bits DDR2 SDRAM sealed in FBGA package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4 bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology.

Published: Mar 21, 2010 |