EDD1216ALTA
Overview
- Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
- Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK
- Quad internal banks operation
- Possible to a
