EDD5104ABTA Overview
The EDD5104AB is a 512M bits Double Data Rate (DDR) SDRAM organized as 33,554,432 words × 4 bits × 4 banks. The EDD5108AB is a 512M bits DDR SDRAM organized as 16,777,216 words × 8 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK.
EDD5104ABTA Key Features
- 2.5 V power supply: VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V
- Data Rate: 333Mbps/266Mbps (max.)
- Double Data Rate architecture; two data transfers per clock cycle
- Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver
- Data inputs, outputs, and DM are synchronized with DQS
- 4 internal banks for concurrent operation
- DQS is edge aligned with data for READs; center aligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS