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EDS2532AABJ-75 - 256M bits SDRAM

Features

  • B DQ28 VDDQ VSSQ C VSSQ DQ27 DQ25 D VSSQ DQ29 DQ30 E VDDQ DQ31 NC A3 A6 NC A9 NC VSS F VSS DQM3.
  • ×32 organization.
  • Single pulsed /RAS.
  • Burst read/write operation and burst read/single write operation capability.
  • Byte control by DQM Document No. E0508E40 (Ver. 4.0) Date Published December 2005 (K) Japan Printed in Japan URL: http://www. elpida. com L G A4 A5 A8 CKE NC H A7 J CLK K DQM1 /WE DQM0 DQ7 VSSQ DQ5 VDDQ DQ3 VDDQ Pr L M N P R VDDQ DQ8 VSSQ.

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Datasheet preview – EDS2532AABJ-75

Datasheet Details

Part number EDS2532AABJ-75
Manufacturer Elpida Memory
File Size 700.17 KB
Description 256M bits SDRAM
Datasheet download datasheet EDS2532AABJ-75 Datasheet
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Full PDF Text Transcription

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www.DataSheet4U.com DATA SHEET 256M bits SDRAM EDS2532AABJ-75 (8M words × 32 bits) Specifications • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V • Clock frequency: 133MHz (max.) • 2KB page size ⎯ Row address: A0 to A11 ⎯ Column address: A0 to A8 • Four internal banks for concurrent operation • Interface: LVTTL • Burst lengths (BL): 1, 2, 4, 8, full page • Burst type (BT): ⎯ Sequential (1, 2, 4, 8, full page) ⎯ Interleave (1, 2, 4, 8) • /CAS Latency (CL): 2, 3 • Precharge: auto precharge operation for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 4096 cycles/64ms ⎯ Average refresh period: 15.
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