EDS2532EEBH-75 Datasheet | Elpida Memory

Description The EDS2532EEBH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 90-ball FBGA. Pin Configurations /xxx indicate active low signal. 90-ball FBGA 1 2 3 4 5 6 7 8 9 DQ26 DQ24 VSS VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC A2 A10 NC BA0 /CAS DQ6 DQ1 Features - - - - - - 1.8V power supply Clock frequency: 133MHz (max.) LVCMOS interface Single pulsed /RAS ×32 organization 4 banks can operate simultaneously and independently - Burst read/write operation and burst read/single write operation capability - Programmable burst length (BL): 1, 2, 4, 8 and full page - 2 variations of burst sequence  Sequential (BL = 1, 2, 4, 8, full page)  Interleave (BL = 1, 2, 4, 8) - Programmable /CAS latency (CL): 2, 3 - Programmable driver strength: Half , Quarter - Byte control by DQM - Address  4K Row address /512 column address - Refresh cycles  4096 refresh cycles/64ms - 2 variations of refresh  Auto refresh  Self refresh - FBGA package with lead free solder (Sn-Ag-Cu)  Ro HS pliant DQ28 VDDQ VSSQ VSSQ DQ27 DQ25 VSSQ DQ29 DQ30 VDDQ DQ31 NC A3 A6 NC A9 DQ16 VSSQ DQM2 VDD A0 BA1 /CS A1 A11 /RAS VSS...