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EDS2532EESL-75 - 256M bits SDRAM

Features

  • B VSSQ DQ15 DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 VDDQ DQ5 DQ4 DQ6 C VDDQ DQ13 DQ14 D DQ11 DQ12 E DQ9 DQ10 VSSQ F DQ8 VDDQ VSSQ DQ7 VDD DQM0 /WE /CAS /RAS A9 A7 BA0 A10 A11 BA1 A1 VDD DQM2 NC NC A0 A2 G CLK DQM1 VSS.
  • ×32 organization.
  • Single pulsed /RAS.
  • Burst read/write operation and burst read/single write operation capability.
  • Byte control by DQM Document No. E0888E10 (Ver. 1.0) Date Published March 2006 (K) Japan Printed in Japan URL: http://www. elpida. com L.

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Datasheet preview – EDS2532EESL-75

Datasheet Details

Part number EDS2532EESL-75
Manufacturer Elpida Memory
File Size 792.55 KB
Description 256M bits SDRAM
Datasheet download datasheet EDS2532EESL-75 Datasheet
Additional preview pages of the EDS2532EESL-75 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com DATA SHEET 256M bits SDRAM EDS2532EESL-75 (8M words × 32 bits) Specifications • Density: 256M bits • Organization  2M words × 32 bits × 4 banks • Package: 92-ball FBGA  Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Clock frequency: 133MHz (max.) • 2KB page size  Row address: A0 to A11  Column address: A0 to A8 • Four internal banks for concurrent operation • Interface: LVCMOS • Burst lengths (BL): 1, 2, 4, 8, full page • Burst type (BT):  Sequential (1, 2, 4, 8, full page)  Interleave (1, 2, 4, 8) • /CAS Latency (CL): 2, 3 • Precharge: auto precharge operation for each burst access • Driver strength: half/quarter • Refresh: auto-refresh, self-refresh • Refresh cycles: 4096 cycles/64ms  Average refresh period: 15.
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