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EDS2532JEBH-75 - 256M bits SDRAM

Description

The EDS2532JEBH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks.

All inputs and outputs are synchronized with the positive edge of the clock.

It is packaged in 90-ball FBGA.

Features

  • 2.5V power supply Clock frequency: 133MHz (max. ) LVCMOS interface Single pulsed /RAS ×32 organization 4 banks can operate simultaneously and independently.
  • Burst read/write operation and burst read/single write operation capability.
  • Programmable burst length (BL): 1, 2, 4, 8 and full page.
  • 2 variations of burst sequence  Sequential (BL = 1, 2, 4, 8, full page)  Interleave (BL = 1, 2, 4, 8).
  • Programm.

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Datasheet preview – EDS2532JEBH-75

Datasheet Details

Part number EDS2532JEBH-75
Manufacturer Elpida Memory
File Size 764.53 KB
Description 256M bits SDRAM
Datasheet download datasheet EDS2532JEBH-75 Datasheet
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www.DataSheet4U.com PRELIMINARY DATA SHEET 256M bits SDRAM EDS2532JEBH-75 (8M words × 32 bits) Description The EDS2532JEBH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 90-ball FBGA. Pin Configurations /xxx indicate active low signal. 90-ball FBGA 1 2 3 4 5 6 7 8 9 A DQ26 DQ24 VSS VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC A2 A10 NC BA0 /CAS VDD DQ6 DQ1 Features • • • • • • 2.5V power supply Clock frequency: 133MHz (max.
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