EDS2532JEBH-75 Description
The EDS2532JEBH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 90-ball FBGA.
EDS2532JEBH-75 Key Features
- 2.5V power supply Clock frequency: 133MHz (max.) LVCMOS interface Single pulsed /RAS ×32 organization 4 banks can operat
- Burst read/write operation and burst read/single write operation capability
- Programmable burst length (BL): 1, 2, 4, 8 and full page
- Programmable /CAS latency (CL): 2, 3
- Programmable driver strength: Half , Quarter
- Byte control by DQM
- Address 4K Row address /512 column address
- Refresh cycles 4096 refresh cycles/64ms
- 2 variations of refresh Auto refresh Self refresh
- FBGA package with lead free solder (Sn-Ag-Cu) RoHS pliant