EDS6416CHBH Overview
The EDS6416AHBH, EDS6416CHBH are 64M bits SDRAMs organized as 1,048,576 words × 16 bits × 4 banks. All inputs and outputs are synchronized with .. the positive edge of the clock.
EDS6416CHBH Key Features
- 3.3V and 2.5V power supply Clock frequency: 166MHz/133MHz (max.) Single pulsed /RAS ×16 organization 4 banks can operate
- Burst read/write operation and burst read/single write operation capability
- Programmable /CAS latency (CL): 2, 3
- Byte control by UDQM and LDQM
- Refresh cycles: 4096 refresh cycles/64ms
- 2 variations of refresh Auto refresh Self refresh
- FBGA package with lead free solder (Sn-Ag-Cu) RoHS pliant
- 1 Features