Datasheet Summary
Revision History
Revision 0.1 (Jan. 2013) -First release.
Revision 0.2 (Feb. 2014)
- Update DC current.
Revision 0.3 (Apr. 2014)
- Update Temperature.
Apr. 2014
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.eorex.
1Gb (8M×8Bank×16) Double DATA RATE 2 SDRAM
Features
- JEDEC Standard VDD/VDDQ = 1.8V±0.1V.
- All inputs and outputs are patible with SSTL_18 interface.
- Fully differential clock inputs (CK, /CK) operation.
- Eight Banks
- Posted CAS
- Bust length: 4 and 8.
- Programmable CAS Latency (CL): 5, 6
- Programmable Additive Latency (AL): 0, 1, 2, 3, 4, 5
- Write Latency (WL) =Read Latency (RL) -1.
- Read Latency (RL) = Programmable Additive
Latency (AL) + CAS Latency (CL)
-...