EM44CM1688LBB Description
Revision History Revision 0.1 (Nov. EM44CM1688LBB 1Gb (8M×8Bank×16) Double DATA RATE 2 SDRAM.
EM44CM1688LBB Key Features
- JEDEC Standard VDD/VDDQ = 1.8V±0.1V
- All inputs and outputs are patible with SSTL_18 interface
- Fully differential clock inputs (CK, /CK) operation
- Eight Banks
- Posted CAS
- Bust length: 4 and 8
- Programmable CAS Latency (CL): 5
- Write Latency (WL) =Read Latency (RL) -1
- Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL)
- Bi-directional Differential Data Strobe (DQS)