Datasheet4U Logo Datasheet4U.com

EM44CM1688LBB - 1Gb Double DATA RATE-2 SDRAM

Key Features

  • JEDEC Standard VDD/VDDQ = 1.8V±0.1V.
  • All inputs and outputs are compatible with SSTL_18 interface.
  • Fully differential clock inputs (CK, /CK) operation.
  • Eight Banks.
  • Posted CAS.
  • Bust length: 4 and 8.
  • Programmable CAS Latency (CL): 5.
  • Programmable Additive Latency (AL): 0, 1, 2, 3, 4, 5 & 6.
  • Write Latency (WL) =Read Latency (RL) -1.
  • Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (.

📥 Download Datasheet

Datasheet Details

Part number EM44CM1688LBB
Manufacturer Eorex
File Size 406.08 KB
Description 1Gb Double DATA RATE-2 SDRAM
Datasheet download datasheet EM44CM1688LBB Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
EM4425 RAINFC AUTHENTICITY TRANSPONDER IC EM Microelectronic
EM4444 Read/Write UHF Identification Device EM Microelectronic
EM4450 1-KBit Read/Write Contactless Identification Device EM Microelectronic
EM4469 512 bit Read/Write Contactless Identification Device EM Microelectronic
EM44GT CMOS 4 pad SMD kHz Range EUROQUARTZ limited

Other Datasheets by Eorex

Part Number Description
EM44CM1688LBA 1Gb Double DATA RATE-2 SDRAM
EM44CM1688LBC Double DATA RATE SDRAM
EM44DM0888LBA Double DATA RATE SDRAM
EM428M1644RTA Double DATA RATE SDRAM
EM42AM1684RTC Double DATA RATE SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Revision History Revision 0.1 (Nov. 2010) -First release. EM44CM1688LBB Nov. 2010 1/29 www.eorex.com EM44CM1688LBB 1Gb (8M×8Bank×16) Double DATA RATE 2 SDRAM Features • JEDEC Standard VDD/VDDQ = 1.8V±0.1V. • All inputs and outputs are compatible with SSTL_18 interface. • Fully differential clock inputs (CK, /CK) operation. • Eight Banks • Posted CAS • Bust length: 4 and 8. • Programmable CAS Latency (CL): 5 • Programmable Additive Latency (AL): 0, 1, 2, 3, 4, 5 & 6. • Write Latency (WL) =Read Latency (RL) -1. • Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL) • Bi-directional Differential Data Strobe (DQS). • Data inputs on DQS centers when write. • Data outputs on DQS, /DQS edges when read. • On chip DLL align DQ, DQS and /DQS transition with CK transition.