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Preliminary
EM48AM1644LBB
256Mb (4M×4Bank×16) Synchronous DRAM
Features
• 2 x 4 banks x 2 Mbit x 16 organisation ( Two 128MBit chips stacked in multi-chip package) • Fully Synchronous to Positive Clock Edge • Single 1.8V ±0.1V Power Supply • LVCMOS Compatible with Multiplexed Address • Programmable Burst Length –1/2/4/8/ full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 4/8) • Burst Read with Single-bit Write Operation • Deep Power Down Mode. • Auto Refresh and Self Refresh • Special Function Support.