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EM48AM1684LBA - 256Mb (4M x 4Bank x 16) Synchronous DRAM

Description

The EM48AM1684LBA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 4Meg words x 4 banks by 16 bits.

All inputs and outputs are synchronized with the positive edge of the clock.

Features

  • Fully Synchronous to Positive Clock Edge.
  • VDD/VDDQ= 1.8V +/- 0.15V Power Supply.
  • LVCMOS Compatible with Multiplexed Address.
  • Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page.
  • Programmable CAS Latency (C/L) - 2 or 3.
  • Data Mask (DQM) for Read / Write Masking.
  • Programmable Wrap Sequence.
  • Sequential (B/L = 1/2/4/8/full Page).
  • Interleave (B/L = 1/2/4/8).
  • Burst Read with Single-bit Write Operation.

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Datasheet Details

Part number EM48AM1684LBA
Manufacturer Eorex
File Size 273.30 KB
Description 256Mb (4M x 4Bank x 16) Synchronous DRAM
Datasheet download datasheet EM48AM1684LBA Datasheet

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Full PDF Text Transcription

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eorex Revision History Revision 0.1 (Jul. 2006) - First release. Revision 0.2 (Mar. 2009).. - Add “E” grade Part No. EM48AM1684LBA Mar. 2009 www.eorex.com 1/18 eorex EM48AM1684LBA 256Mb (4M×4Bank×16) Synchronous DRAM Features • Fully Synchronous to Positive Clock Edge • VDD/VDDQ= 1.8V +/- 0.15V Power Supply • LVCMOS Compatible with Multiplexed Address • Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) • Burst Read with Single-bit Write Operation • All Inputs are Sampled at the Rising Edge of the System Clock • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms (7.
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