EM48BM0884VTA Description
All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve.
EM48BM0884VTA Key Features
- Fully Synchronous to Positive Clock Edge
- Single 3.3V ±0.3V Power Supply
- LVTTL patible with Multiplexed Address
- Programmable Burst Length (B/L)
- 1, 2, 4, 8
- Programmable CAS Latency (C/L)
- Data Mask (DQM) for Read / Write Masking
- Programmable Wrap Sequence
- Sequential (B/L = 1/2/4/8/full Page)
- Interleave (B/L = 1/2/4/8)