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EM638325 - 2M x 32 Synchronous DRAM

Description

Table 3.

CLK Input Clock: CLK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CLK.

Features

  • Fast access time: 5.5/5.5 ns.
  • Fast Clock rate: 166/143 MHz.
  • Fully synchronous operation.
  • Internal pipelined architecture.
  • Four internal banks (512K x 32bit x 4bank).
  • Programmable Mode - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst-Read-Single-Write.
  • Burst stop function.
  • Individual byte controlled by DQM0-3.
  • Auto Refresh and Self Refresh.
  • 409.

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Datasheet Details

Part number EM638325
Manufacturer Etron Technology
File Size 564.17 KB
Description 2M x 32 Synchronous DRAM
Datasheet download datasheet EM638325 Datasheet
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Full PDF Text Transcription

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EtronTech EM638325 Etron Confidential 2M x 32 bit Synchronous DRAM (SDRAM) Preliminary (Rev 2.1 Aug. /2010) Features • Fast access time: 5.5/5.5 ns • Fast Clock rate: 166/143 MHz • Fully synchronous operation • Internal pipelined architecture • Four internal banks (512K x 32bit x 4bank) • Programmable Mode - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst-Read-Single-Write • Burst stop function • Individual byte controlled by DQM0-3 • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • Single +3.3V ± 0.3V power supply • Interface: LVTTL • 86-pin 400 x 875 mil plastic TSOP II package, 0.
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