EM6HB08EWUA Datasheet | Etron Technology

Features - JEDEC Standard pliant - Power supplies: VDD & VDDQ = +1.35V (1.283V ~ 1.45V) - Backward patible to VDD & VDDQ = +1.5V ±0.075V - Operating temperature range: (mercial) - Normal operating temperature: TC = 0~85°C - Extended temperature: TC = 85~95°C - Supports JEDEC clock jitter specification - Fully synchronous operation - Fast clock rate: 667/800MHz - Differential Clock, CK & CK# - Bidirectional differential data strobe - DQS & DQS# - 8 internal banks for concurrent operation - 8n-bit prefetch architecture - Pipelined internal architecture - Precharge & active power down - Programmable Mode & Extended Mode registers - Additive Latency (AL): 0, CL-1, CL-2 - Programmable Burst lengths: 4, 8 - Burst type: Sequential / Interleave - Output Driver Impedance Control - Average refresh period - 8192 cycles/64ms (7.8us at 0°C ≦ TC ≦ +85°C) - 8192 cycles/32ms (3.9us at +85°C ≦ TC ≦ +95°C) - Write Leveling - ZQ Calibration - Dynamic ODT (Rtt_Nom & Rtt_WR) - Ro HS pliant - Auto Refresh and Self Refresh - 78-ball 8 x 10.5 x 1.0mm FBGA package - Pb and Halogen Free Overview The 512Mb Double-Data-Rate-3L (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 512Mb chip is organized as 8Mbit x 8 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to ply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V / +0.1V power supply and are available in BGA packages. Table 1. Ordering Information Part Number Clock...