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XRT79L72 - 2-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

Description

4 MICROPROCESSOR INTERFACE 4 TEST AND DIAGNOSTIC 6 GENERAL PURPOSE INPUT AND OUTPUT PINS 7 TRANSMIT SYSTEM SIDE INTERFACE PINS 7 RECEIVE SYSTEM SIDE INTERFACE PINS 24 TRANSMIT LINE SIDE SIGNALS 39 RECEIVE LINE SIDE SIGNALS 41 ELECTRICAL CHARACTERISTICS 46 TABLE 1: DC ELECTRICAL CHARACTERISTICSS 46

Features

  • Integrated T3/E3 Line Interface Unit.
  • Integrated Jitter Attenuator that can be selected either in Receive or Transmit path.
  • Flexible integrated Clock Multiplier that takes single frequency clock and generates either DS3 or E3 frequency.
  • 8/16 bit UTOPIA Level I and II and PPP Multi-PHY Interface operating at 25, 33 or 50 MHz.
  • HDLC Controller that provides the mapping/extraction of either bit or byte mapped encapsulated packet from DS3/E3 Frame.

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Full PDF Text Transcription

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www.DataSheet4U.com xr FEBRUARY 2005 PRELIMINARY XRT79L72 REV. P1.0.2 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC HARDWARE MANUAL The XRT79L72 is a two channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct mapping and cell delineation as well as PPP mapping and Frame processing. For ATM UNI applications, this device provides the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public and private networks at DS3/E3 rates. For Clear-Channel Framer applications, this device supports the transmission and reception of “user data” via the DS3/E3 payload.
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