XRT91L81 Datasheet | Exar

DESCRIPTION The XRT91L81 is a fully integrated SONET/SDH transceiver block for applications in SONET OC-48 allowing the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the highspeed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the ining serial data stream. The chip provides serial-to-parallel and parallel-to-serial converters and 4-bit LVDS system interfaces in both receive and transmit directions. The transmit section includes a 4x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter input clock and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control of the AUTORST pin can automatically recover from FIGURE 1. BLOCK DIAGRAM OF THE XRT91L81 an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET and LOSDET output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section. APPLICATIONS - SONET/SDH-based Transmission Systems - Add/Drop Multiplexers - Cross Connect Equipment - ATM and Multi-Service Switches, Routers and Switch/Routers - DSLAMS - SONET/SDH Test Equipment - DWDM Termination Equipment - Optical Modules and Sub-Systems OC-48 TRANSCEIVER FIFO_RST FIFO_AUTORST Tx DI0P/N Tx DI1P/N Tx DI2P/N Tx DI3P/N Tx CLKIP/N TXPCLKOP/N TXCLKO16P/N TRITXCLKO16 WP 4x9 FIFO PISO (Parallel Input Serial Output) TXOP/N Re-Timer 0 1 TXO2P/N CMU RLOOPP DLOOP RLOOPS TXO2DIS TXO2SEL Rx DO0P/N Rx DO1P/N Rx DO2P/N Rx DO3P/N Rx CLKP/N RXCLK16P/N DISRD SIPO...