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N‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
S2 S2 S2 G2
N‐CH‐Q1 N‐CH‐Q2
BVDSS
30V
30V
D2 / S1
RDSON (MAX.) 9.5mΩ 9.5mΩ
ID
15A
15A
D1
EMB09A3HP
UIS, Rg 100% Tested
D1 D1 D1 PIN 1 (G1)
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
LIMITS
UNIT
Q1
Q2
Gate‐Source Voltage
Continuous Drain Current Pulsed Drain Current1
TC = 25 °C TC = 100 °C
Avalanche Current
Avalanche Energy
L = 0.1mH, RG=25Ω
Repetitive Avalanche Energy2
L = 0.05mH
Power Dissipation
TC = 25 °C TC = 100 °C
Operating Junction & Storage Temperature Range
VGS ID
IDM IAS EAS EAR PD
Tj, Tstg
±20
±20
V
15
15
12
12
A
60
60
15
15
11.25 5.62
11.25 mJ
5.