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Dual Asymmetric N‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
N‐CH‐Q1 N‐CH‐Q2
BVDSS
30V
30V
RDSON (MAX.)
15.5mΩ 12.5mΩ
ID
9A
10A
UIS, Rg 100% Tested Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage
Continuous Drain Current Pulsed Drain Current1
TC = 25 °C TC = 100 °C
Avalanche Current
Avalanche Energy
L = 0.1mH, ID=10A, RG=25Ω
Repetitive Avalanche Energy2
L = 0.05mH
Power Dissipation
TC = 25 °C TC = 100 °C
Operating Junction & Storage Temperature Range
VGS ID
IDM IAS EAS EAR PD
Tj, Tstg
EMB12K03GP
LIMITS
±20
±20
9
10
6
7
36
40
12
12
5
5
2.5
2.5
2
1.
EMB12K03GP Datasheet
