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74LS194A - 4-Bit Bidirectional Universal Shift Register

Download the 74LS194A datasheet PDF. This datasheet also covers the 74LS194 variant, as both devices belong to the same 4-bit bidirectional universal shift register family and are provided as variant models within a single manufacturer datasheet.

General Description

This bidirectional shift register is designed to incorporate virtually all of the

Key Features

  • a system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both m.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74LS194_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM74LS194A 4-Bit Bidirectional Universal Shift Register August 1986 Revised March 2000 DM74LS194A 4-Bit Bidirectional Universal Shift Register General Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, HIGH.