Datasheet Details
| Part number | 74LS74A |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 66.39 KB |
| Description | Dual Positive-Edge-Triggered D Flip-Flops |
| Datasheet | 74LS74A-FairchildSemiconductor.pdf |
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Overview: DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and plementary Outputs August 1986 Revised March 2000 DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and plementary.
| Part number | 74LS74A |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 66.39 KB |
| Description | Dual Positive-Edge-Triggered D Flip-Flops |
| Datasheet | 74LS74A-FairchildSemiconductor.pdf |
|
|
|
This device contains two independent positive-edge-triggered D flip-flops with plementary outputs.
The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse.
The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock.
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
 |
74LS74A | DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP | Motorola |
 |
74LS74A | Dual Positive-Edge-Triggered D Flip-Flops | National Semiconductor |
 |
74LS74A | Dual D-Type Positive-Edge-Triggered Flip-Flop | Texas Instruments |
 |
74LS74 | LOW-POWER SCHOTTKY | ON Semiconductor |
 |
74LS74 | Dual D-type Positive Edge-triggered Flip-Flops | Hitachi Semiconductor |
| Part Number | Description |
|---|---|
| 74LS73 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
| 74LS73A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
| 74LS75 | Quad Latch |
| 74LS00 | Quad 2-Input NAND Gate |
| 74LS02 | Quad 2-Input NOR Gate |
| 74LS03 | Quad 2-Input NAND Gates |
| 74LS04 | Hex Inverting Gates |
| 74LS05 | Hex Inverters |
| 74LS08 | Quad 2-Input AND Gates |
| 74LS09 | Quad 2-Input AND Gates |