Datasheet Details
| Part number | 74LS73 |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 53.28 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
| Datasheet | 74LS73_FairchildSemiconductor.pdf |
|
|
Overview: DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and plementary Outputs August 1986 Revised March 2000 DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and.
| Part number | 74LS73 |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 53.28 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
| Datasheet | 74LS73_FairchildSemiconductor.pdf |
|
|
|
This device contains two independent negative-edge-triggered J-K flip-flops with plementary outputs.
The J and K data is processed by the flip-flops on the falling edge of the clock pulse.
The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse.
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
 |
74LS73 | Dual J-K Flip-Flops | Hitachi Semiconductor |
 |
74LS73 | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | Motorola |
|
74LS73A | Dual J-K Flip-Flops | Hitachi Semiconductor |
| Part Number | Description |
|---|---|
| 74LS73A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
| 74LS74A | Dual Positive-Edge-Triggered D Flip-Flops |
| 74LS75 | Quad Latch |
| 74LS00 | Quad 2-Input NAND Gate |
| 74LS02 | Quad 2-Input NOR Gate |
| 74LS03 | Quad 2-Input NAND Gates |
| 74LS04 | Hex Inverting Gates |
| 74LS05 | Hex Inverters |
| 74LS08 | Quad 2-Input AND Gates |
| 74LS09 | Quad 2-Input AND Gates |