74LS73
Overview
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse.
| Part | 74LS73 |
|---|---|
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
| Manufacturer | Fairchild Semiconductor |
| Size | 53.28 KB |
Related Datasheets
| Part Number | Manufacturer | Description |
|---|---|---|
| 74LS73 | Hitachi Semiconductor | Dual J-K Flip-Flops |
| 74LS73A | Hitachi Semiconductor | Dual J-K Flip-Flops |
| 74LS73 | Motorola Semiconductor | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| 74LS74 | Hitachi Semiconductor | Dual D-type Positive Edge-triggered Flip-Flops |
| 74LS74 | Texas Instruments | Dual D-Type Positive-Edge-Triggered Flip-Flop |