74LS73 Description
SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum...
74LS73 Key Features
- l Q L q L H q Q H q H L q Ceramic Plastic SOIC MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE CD Reset (Clea
- LOGIC SYMBOL 14 1 3 J CP Q 12 7 5 J CP Q 9 H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don