| Part Number | 74LS73 Datasheet |
|---|---|
| Manufacturer | Fairchild Semiconductor |
| Overview | This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The cloc. uit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs CLR L H H H H H CLK X ↓ ↓ ↓ ↓ H J X L H L. |
74LS73 Datasheet and Specifications PDF
The 74LS73 is a Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops.
| Part Number | 74LS73 Datasheet |
|---|---|
| Description | Dual J-K Flip-Flops |
| Manufacturer | Hitachi Semiconductor |
| Overview | Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference val. rty rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be su. |
| Part Number | 74LS73 Datasheet |
|---|---|
| Description | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| Manufacturer | Motorola Semiconductor |
| Overview | SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the in. et) Load “1” (Set) Hold L H H H H J X h l h l LOGIC SYMBOL 14 1 3 J CP Q 12 7 5 J CP Q 9 H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time l, h (q) = prior to the HIGH to LO. |