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NDP6030L - N-Channel Logic Level Enhancement Mode Field Effect Transistor

Datasheet Summary

Description

These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

Features

  • 52 A, 30 V. RDS(ON) = 0.0135 Ω @ VGS=10 V RDS(ON) = 0.020 Ω @ VGS=4.5 V. Critical DC electrical parameters specified at elevated temperature. Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. High density cell design for extremely low RDS(ON). 175°C maximum junction temperature rating. _______________________________________________________________________________ D G S Absolute Maximum Ratings Symbol VDSS VGSS ID Parameter Drain-Sour.

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Datasheet Details

Part number NDP6030L
Manufacturer Fairchild
File Size 357.87 KB
Description N-Channel Logic Level Enhancement Mode Field Effect Transistor
Datasheet download datasheet NDP6030L Datasheet
Additional preview pages of the NDP6030L datasheet.

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Full PDF Text Transcription

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June 1996 NDP6030L / NDB6030L N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as DC/DC converters and high efficiency switching circuits where fast switching, low in-line power loss, and resistance to transients are needed. Features 52 A, 30 V. RDS(ON) = 0.0135 Ω @ VGS=10 V RDS(ON) = 0.020 Ω @ VGS=4.5 V. Critical DC electrical parameters specified at elevated temperature.
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