NDS356P Datasheet | Fairchild Semiconductor

Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook puter power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Features -1.1 A, -20V. RDS(ON) = 0.3Ω @ VGS = -4.5V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. pact industry standard SOT-23 surface mount package. Absolute Maximum Ratings Symbol VDSS VGSS ID PD...