NDS352AP - P-Channel Logic Level Enhancement Mode Field Effect Transistor

Product Overview

Fairchild

Datasheet Details

Part number	NDS352AP
Manufacturer	Fairchild
File Size	78.57 KB
Description	P-Channel Logic Level Enhancement Mode Field Effect Transistor
Datasheet	NDS352AP Datasheet
Additional preview pages of the NDS352AP datasheet.

Product details

Description

These P -Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

Features

-0.9 A, -30 V. RDS(ON) = 0.5 Ω @ VGS = -4.5 V RDS(ON) = 0.3 Ω @ VGS = -10 V. Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ________________________________________________________________________________ D G S Absolute Maximum Ratings Symbol VDSS VGSS ID Parameter Drain-Source Voltage.

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Published: May 12, 2005 |