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56F8023 - 16-bit Digital Signal Controllers

General Description

Initial public release.

In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years).

In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.

In Table 10-12, changed the typical relaxat

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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56F8033/56F8023 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8023 Rev. 6 02/2010 freescale.com Version History Rev. 0 Rev. 1 Rev. 2 Rev. 3 Rev. 4 Rev. 5 Document Revision History Description of Change Initial public release. • In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). • In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. • In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz. • Changed input propagation delay values in Table 10-20 as follows: Old values: 1 μs typical, 2 μs maximum New values: 35 ns typical, 45 ns maximum In Table 10-19, changed the maximum ADC internal clock frequency from 8 MHz to 5.