MCF52274 Datasheet | Freescale Semiconductor

Features - Version 2 Cold Fire® Core with EMAC - Up to 159 Dhrystone 2.1 MIPS @ 166.67 MHz - 8 Kbytes configurable cache (instruction only, data only, or split instruction/data) - 128 Kbytes internal SRAM - Support for booting from SPI-patible flash, EEPROM, and FRAM devices - Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters - 16 channel DMA controller - 16- or 32-bit SDR/DDR controller - USB 2.0 On-the-Go controller - Liquid crystal display controller with support up to 800 × 600 pixels - ADC and touchscreen controller - Flex CAN module - 4 32-bit timers with DMA support - DMA supported serial peripheral interface (DSPI) - 3 UARTs - I2C bus interface - Synchronous serial interface (SSI) - Plus-width modulator (PWM) - Real-time clock (RTC) - Two programmable interrupt controllers (PIT) This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2008. All rights reserved. Preliminary- Subject to Change Without Notice Table of Contents MCF5227x Family parison - - - - . . . .4 Ordering Information- - - - - - . . .5 Hardware Design Considerations - - - - . . .5 3.1 PLL Power Filtering- - - - - . . . .5 3.2 USB Power Filtering - - - - - . . .5 3.3 ADC Power Filtering - - - - - . . .6 3.4 Supply Voltage Sequencing -...