Datasheet4U Logo Datasheet4U.com

MM912F634 - Integrated S12 Based Relay Driver

General Description

6 2.2 MCU Die Signal Properties

Key Features

  • 16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM.
  • Background Debug (BDM) & Debug Module (DBG).
  • Die to Die bus interface for transparent memory mapping.
  • On-chip oscillator & two independent watchdogs.
  • LIN 2.1 Physical Layer Interface with integrated SCI.
  • www. DataSheet4U. net Six digital MCU GPIOs shared with SPI (PA5…0).
  • 10-Bit, 15 Channel - Analog to Digital Converter (ADC).
  • 16-Bit, 4 Channel - Timer Module (TIM16B4C).

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MM912I637 Intelligent integrated precision battery sensor NXP
MM912I637AM2EP Intelligent integrated precision battery sensor NXP
MM912I637AV1EP Intelligent integrated precision battery sensor NXP
MM912J637 Intelligent integrated precision battery sensor NXP
MM912J637AM2EP Intelligent integrated precision battery sensor NXP

Other Datasheets by Freescale Semiconductor (now NXP Semiconductors)

Part Number Description
MM912G634CM1AE Integrated S12 Based Relay Driver
MM912G634CV1AE Integrated S12 Based Relay Driver
MM912G634CV2AP Integrated S12 Based Relay Driver
MM912H634CM1AE Integrated S12 Based Relay Driver
MM912H634CV1AE Integrated S12 Based Relay Driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Freescale Semiconductor Advanced Information Document Number: MM912F634 Rev. 5.0, 11/2010 Integrated S12 Based Relay Driver with LIN The MM912F634 is an integrated single package solution that integrates an HCS12 microcontroller with a SMARTMOS analog control IC. The Die to Die Interface (D2D) controlled analog die combines system base chip and application specific functions, including a LIN transceiver. Features • 16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM • Background Debug (BDM) & Debug Module (DBG) • Die to Die bus interface for transparent memory mapping • On-chip oscillator & two independent watchdogs • LIN 2.1 Physical Layer Interface with integrated SCI •www.DataSheet4U.