29F800 Datasheet | Fujitsu Media Devices Limited

FEATURES - Single 5.0 V read, write, and erase Minimizes system level power requirements - patible with JEDEC-standard mands Uses same software mands as E2PROMs - patible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type) 44-pin SOP (Package suffix: PF) - Minimum 100,000 write/erase cycles - High performance 55 ns maximum access time - Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes. Any bination of sectors can be concurrently erased. Also supports full chip erase. - Boot Code Sector Architecture T = Top sector B = Bottom sector - Embedded Erase TM Algorithms Automatically pre-programs and erases the chip or any sector - Embedded Program TM Algorithms Automatically writes and verifies data at specified address - Data Polling and Toggle Bit feature for detection of program or erase cycle pletion - Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle pletion - Low Vcc write inhibit ≤ 3.2 V - Erase Suspend/Resume Suspends the erase operation to allow a read data in another sector within the same device - Hardware RESET pin Resets internal state machine to the read mode - Sector protection Hardware method disables any bination of sectors from write or erase operations - Temporary sector unprotection Temporary sector unprotection via the RESET pin. Embedded Erase TM and Embedded Program TM are trademarks of Advanced Micro Devices, Inc. MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90 s PACKAGE 48-pin TSOP(I) Marking Side 44-pin SOP Marking Side Marking Side (FPT-48P-M19) (FPT-48P-M20) (FPT-44P-M16) MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90 s GENERAL DESCRIPTION The MBM29F800TA/BA is a 8M-bit, 5.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each. The MBM29F800TA/BA is offered in a 48-pin TSOP(I) and 44-pin SOP packages. This device is designed to be programmed in-system with the...