MBM29F040C-90 Datasheet PDF - Fujitsu Media Devices 4M (512K X 8) BIT FLASH MEMORY Specs

MBM29F040C-90 - 4M (512K X 8) BIT FLASH MEMORY

This page provides the datasheet information for the MBM29F040C-90, a member of the MBM29F040C 4M (512K X 8) BIT FLASH MEMORY family.

Datasheet Summary

Description

The MBM29F040C is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each.

The MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package.

This device is designed to be programmed in-system with the standard system 5.0 V VCC supply.

Features

www. DataSheet4U. com.
Single 5.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: PD) 32-pin TSOP(I) (Package suffix: PF) 32-pin TSOP(I) (Package suffix: PFTN.
Normal Bend Type, PFTR.
Re.

Datasheet Details

Part number	MBM29F040C-90
Manufacturer	Fujitsu Media Devices
File Size	437.81 KB
Description	4M (512K X 8) BIT FLASH MEMORY
Datasheet	MBM29F040C-90 Datasheet
Additional preview pages of the MBM29F040C-90 datasheet.

📁 Similar Datasheet

MBM29F040A-12 - FLASH MEMORY 4M 512K x 8 BIT (Fujitsu)

MBM29F040A-70 - FLASH MEMORY 4M 512K x 8 BIT (Fujitsu)

MBM29F040A-90 - FLASH MEMORY 4M 512K x 8 BIT (Fujitsu)

MBM29F002BC-55 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29F002BC-70 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29F002BC-90 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29F002TC-55 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29F002TC-70 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29F002TC-90 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29F004BC-70 - FLASH MEMORY CMOS 4M (512K x 8) BIT (Fujitsu)

Full PDF Text Transcription

Click to expand full text

FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 4M (512K × 8) BIT DS05-20842-4E MBM29F040C-55/-70/-90 s FEATURES • • • www.DataSheet4U.com • • • • • • • • • Single 5.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: PD) 32-pin TSOP(I) (Package suffix: PF) 32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) Minimum 100,000 write/erase cycles High performance 55 ns maximum access time Sector erase architecture 8 equal size sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase.

Published: May 11, 2015 |