MBM29LV001TC Datasheet PDF - Fujitsu Media Devices 1M (128K x 8) BIT Specs

MBM29LV001TC - 1M (128K x 8) BIT

This page provides the datasheet information for the MBM29LV001TC, a member of the MBM29LV001BC 1M (128K x 8) BIT family.

Datasheet Summary

Description

The MBM29LV001TC/BC are a 1M-bit, 3.0 V-only Flash memory organized as 128K bytes of 8 bits each.

The MBM29LV001TC/BC are offered in a 32-pin TSOP(I) and 32-pin PLCC packages.

These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply.

Features

Single 3.0 V read, program, and erase Minimizes system level power requirements.
Compatible with JEDEC-standard commands Uses same software commands as E2PROMs.
Compatible with JEDEC-standard world-wide pinouts 32-pin TSOP(I) (Package suffix: PFTN.
Normal Bend Type, PFTR.
Reversed Bend Type) 32-pin PLCC (Package suffix: PD).
Minimum 100,000 program/erase cycles.
High performance 55 ns maximum access time.
Sector erase archi.

Datasheet Details

Part number	MBM29LV001TC
Manufacturer	Fujitsu Media Devices
File Size	421.17 KB
Description	1M (128K x 8) BIT
Datasheet	MBM29LV001TC Datasheet
Additional preview pages of the MBM29LV001TC datasheet.

📁 Similar Datasheet

MBM29LV001TC-55 - 1M (128K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29LV001TC-70 - 1M (128K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29LV001BC-55 - 1M (128K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29LV001BC-70 - 1M (128K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29LV002BC-12 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29LV002BC-70 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29LV002BC-90 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29LV002TC-12 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29LV002TC-70 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

MBM29LV002TC-90 - 2M (256K x 8) BIT FLASH MEMORY (Fujitsu)

Full PDF Text Transcription

Click to expand full text

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20861-3E FLASH MEMORY CMOS 1M (128K × 8) BIT MBM29LV001TC-55/-70/MBM29LV001BC-55/-70 s FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 32-pin PLCC (Package suffix: PD) • Minimum 100,000 program/erase cycles • High performance 55 ns maximum access time • Sector erase architecture One 8K byte, two 4K bytes, and seven 16K bytes Any combination of sectors can be concurrently erased.

Published: Oct 2, 2005 |