MBM29SL800BD Datasheet Text
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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20871-5E
FLASH MEMORY
CMOS
8 M (1 M × 8/512 K × 16) BIT
MBM29SL800TD/BD-10/12 s DESCRIPTION
The MBM29SL800TD/BD are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512 Kwords of 16 bits each. The MBM29SL800TD/BD are offered in a 48-pin TSOP (I) , 48-ball FBGA and 48-ball SCSP packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINE UP
Part No. Ordering Part No. VCC = +2.0 V ± 0.2 Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MBM29SL800TD/MBM29SL800BD
- 10 100 100 35
- 12 120 120 50 s PACKAGES
48-pin Plastic TSOP (I)
Marking Side
48-pin Plastic TSOP (I)
48-pin Plastic FBGA
48-pin Plastic SCSP
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-48P-M12)
(WLP-48P-M03)
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(Continued)
The standard MBM29SL800TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE) , write enable (WE) , and output enable (OE) controls. The MBM29SL800TD/BD are pin and mand set patible with JEDEC standard E2PROMs. mands are written to the mand register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V...
