MB8264-15 Overview
The Fujitsu MB8264 is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words. The design Is optimized for high-speed, high performance applications such as mainframe memory, buffer memory, peripheral storage and environments where low power dissipation and pact layout are required. Multiplexed row and column address inputs permit the MB8264 to be housed In a standard 16-pln DIP.
MB8264-15 Key Features
- Sillcon-gate, Double Poly NMOS, single transistor cell
- Row access time: 150ns Max (MB8264-15) 200ns Max (MB8264-20)
- Cycle time: 270ns Min (MB8264-15) 330ns Min (MB8264-20)
- Low power: 22 mW Max Standby 275 mW Max Active (MB8264-15) 248 mW Max Active (MB8264-20)
- !:10% tolerance on +5V Supply
- On-chlp substrate bias generator
- All Inputs TTL patible, low capacitive load
- Three-state TTL patible output
- "Gated" CAS .128 refresh cycles
- mon 110 capability using "Early Write" operation